1. Field of the Invention
The present invention relates to automated integrated circuit design tools, more particularly to netlist editing procedures.
2. State of the Art
In a computer-aided engineering (CAE) environment, integrated circuits are usually created via schematic or a high-level language, such as VHDL, and then translated into a symbolic representation of the integrated circuit in the form of a netlist.
Generally speaking, a netlist provides information concerning the number and types of elements in a circuit and the manner in which they are interconnected. For example, a netlist might include a list of circuit element terminals connected on a common net. Thus, if a first AND gate receives one input from an invertor and a second input from an OR gate, and provides an output to both a NOR gate and a second AND gate, the netlist would indicate that a first net connects an output connector of the invertor and one input connector of the first AND gate. A second net would connect an output connector of the OR gate and another input connector of the first AND gate. Finally, a third net would connect an output connector of the first AND gate, an input connector of the NOR gate, and and input connector of the second AND gate. It should be understood, however, that netlists are not restricted to use in describing logic diagrams. In a netlist, the interconnected circuit elements, typically referred to as cells, may be as simple as a resistor, or as complex as a microprocessor. Furthermore, netlists also contain attribute information, for example how wide a physical wire is to be or how much capacitance is to be allowed on a wire.
One way in which a netlist is generated is as a result of logic synthesis. Stated briefly, a logic synthesis tool may receive as an input a Boolean function expressed in terms of a state table, and generate a netlist including the logic circuits and the interconnections which would implement the given Boolean function.
A netlist could also be produced as an output from a typical datapath compiler. A datapath compiler will usually receive a high-level schematic as an input, and produce a netlist output providing more detailed circuit information. For example, a high-level schematic may include a datapath element such as a scan logic chain. The datapath compiler may produce a standard netlist representing a scan logic chain, which standard netlist would be incorporated into the netlist of the overall circuit.
Often, circuit changes must be made to the netlist. These changes may be needed due to last-minute changes to the function of the circuit, special testability logic, clock skew requirements, or other reasons.
Conventionally, there are three alternative method for modifying a netlist:
1) Change the original source (e.g., the schematic or VHDL specification) and generate a new netlist. This option is not always practical because optimizations and modifications may have already been performed on the netlist before the need for custom modification arises. For example, a design tool may have been used to automatically insert test logic into a circuit. Reverting to the original schematic or VHDL specification would cause such changes to be lost. PA1 2) Use a design tool (such as a MakeSchematic tool available from COMPASS Design Automation of San Jose, Calif.) to translate the netlist into a schematic, change the schematic, and generate a new netlist. The problem with this approach is that the resulting schematic is invariably crowded and extremely difficult to manipulate. Furthermore, making a schematic from a large netlist is not always possible. PA1 3) Edit the netlist using a text editor. Such editing is very prone to error. The netlist format is often undocumented, requiring considerable guesswork. A simple typing mistake may result in the entire netlist being corrupted.
Many CAE vendors have software tools that interact with the netlist. Such programs have their own internal netlist editing programming functions. One such tool is Test Assistant, available from COMPASS. The CAD Framework Initiative (CFI) defines an interface standard for interfacing between netlist editing procedures and CAE programs. Existing netlist editing procedures, however, have been used only inside design programs in a manner dictated by the program.
This situation is illustrated in FIG. 1. A program 10 (such as Test Assistant) provides for netlist modification in response to user selections. The user selections are limited to a high level, however, and the resulting netlist modifications performed are fixed by the program. For example, in Test Assistant, a user may select scan path ordering, in response to which Test Assistant automatically performs scan logic insertion. To perform scan logic insertion, Test Assistant calls upon a collection of netlist editing procedures (or netlist utilities), including, for example, such procedures as addInstance, connectWire, disconnectWire, etc. These procedures are used to operate upon a source netlist in accordance with the fixed netlist modification program to produce a modified netlist.
After the fixed netlist modification program has been run, the user may in some instances need to add custom logic, modify clock trees, or otherwise modify the netlist. However, the user is not allowed to "bypass" the fixed netlist modification program in order to modify the netlist directly using low-level netlist editing procedures. "Tweaking" the netlist has therefore been problematic.